ASIC Physical Design (Back-end)

Need a customized chip for your applications?

Ulepus offers ASIC physical design and verification of block and/or chip level projects.

  • Floorplanning.

  • Place and Route (P&R).

  • Clock Tree Synthesis (CTS).

  • Timing closure, and area & power optimization.

  • Static & Dynamic power/rail analysis.

  • Electromigration (EM) analysis.

  • Physical verifications (DRC, LVS, ERC, ANT).

  • Logic Equivalence Check (LEC).