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ASIC Physical Design (Back-end)
Need a customized chip for your applications?
Ulepus offers ASIC physical design and verification of block and/or chip level projects.
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Floorplanning.
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Place and Route (P&R).
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Clock Tree Synthesis (CTS).
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Timing closure, and area & power optimization.
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Static & Dynamic power/rail analysis.
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Electromigration (EM) analysis.
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Physical verifications (DRC, LVS, ERC, ANT).
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Logic Equivalence Check (LEC).
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