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ASIC/FPGA Digital Design (Front-end)
Order a tailor-made digital IP block to satisfy your needs.
Ulepus offers:
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Functional specification.
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Digital logic design (RTL).
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Synthesis, timing sign-off, low power design.
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Logic verification using System Verilog and UVM.
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Constrained random testing, control oriented verification.
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Functional and code coverage analysis.
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UVM based VIP development.
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DO-254 certifiable designs.
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