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ASIC/FPGA Digital Design (Front-end)

Order a tailor-made digital IP block to satisfy your needs. 

​Ulepus offers:

  • Functional specification.

  • Digital logic design (RTL).

  • Synthesis, timing sign-off, low power design.

  • Logic verification using System Verilog and UVM.

  • Constrained random testing, control oriented verification.

  • Functional and code coverage analysis.

  • UVM based VIP development.

  • DO-254 certifiable designs. 

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