About the Role
We are looking for ASIC Design Engineers to join our team and contribute to advanced chip development projects. In this role, you will be responsible for the full ASIC flow—from RTL design to synthesis, static timing analysis, and design-for-test (DFT). You will work closely with cross-functional teams to deliver high-performance and power-efficient designs in advanced technology nodes.
Responsibilities:
RTL development using Verilog/SystemVerilog
Synthesis, linting, and static timing analysis
Integration of IPs and top-level design
Collaborating with physical design and verification teams
Writing and maintaining design documentation
Minimum Qualifications:
Bachelor’s degree in Electrical or Electronics Engineering
Solid understanding of digital design fundamentals
Proficiency in Verilog/SystemVerilog
Familiarity with EDA tools for synthesis and STA
Strong analytical and communication skills
Preferred Qualifications:
Experience with ASIC design flow in advanced nodes (e.g., 16nm, 7nm)
Knowledge of UPF, DFT, and clock domain crossing (CDC) techniques
Familiarity with industry-standard tools (Synopsys, Cadence, Siemens EDA)
Experience in working with version control and scripting (TCL, Python)
Exposure to tapeout or signoff processes
📩 To apply, send your CV to hr@ulepus.com